Retrieved from DBLP. Full publications is available at Google Scholar.
Journals
-
“Design-for-reliability and on-the-fly fault tolerance procedure for
paper-based digital microfluidic biochips with multiple faults.”
Integr. (2023)
-
“Design Automation for Continuous-Flow Lab-on-a-Chip Systems: A One-Pass
Paradigm.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2023)
-
“Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip
Systems.”
ACM Comput. Surv. (2022)
-
“Mixer-Based Washing Methods for Programmable Microfluidic Devices.”
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2022)
-
“Guest Editorial: Trustworthy AI.”
ACM J. Emerg. Technol. Comput. Syst. (2022)
-
“Flow-Based Microfluidic Biochips With Distributed Channel Storage:
Synthesis, Physical Design, and Wash Optimization.”
IEEE Trans. Computers (2022)
-
“JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum
Circuits.”
IEEE Trans. Computers (2022)
-
“PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based
Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2022)
-
“Contamination-Aware Synthesis for Programmable Microfluidic Devices.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2022)
-
“MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic
Biochips With Strictly Constrained Control Ports.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2022)
-
“Demand-Driven Multi-Target Sample Preparation on Resource-Constrained
Digital Microfluidic Biochips.”
ACM Trans. Design Autom. Electr. Syst. (2022)
-
“DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic
Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2021)
-
“Splitter-Aware Multiterminal Routing With Length-Matching Constraint
for RSFQ Circuits.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2021)
-
“Placement of Digital Microfluidic Biochips via a New Evolutionary
Algorithm.”
ACM Trans. Design Autom. Electr. Syst. (2021)
-
“URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale
Sample Delivery Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
-
“Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital
Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
-
“Timing-Driven Flow-Channel Network Construction for Continuous-Flow
Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
-
“Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic
Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
-
“Test Generation for Flow-Based Microfluidic Biochips With General
Architectures.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
-
“Microfluidic Design for Concentration Gradient Generation Using Artificial
Neural Network.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
-
“Multitarget Sample Preparation Using MEDA Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
-
“Lookup Table-Based Fast Reliability-Aware Sample Preparation Using
Digital Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
-
“How Secure Is Split Manufacturing in Preventing Hardware Trojan?.”
ACM Trans. Design Autom. Electr. Syst. (2020)
-
“Scheduling algorithms for reservoir- and mixer-aware sample preparation
with microfluidic biochips.”
Integr. (2019)
-
“Co-placement optimization in sensor-reusable cyber-physical digital
microfluidic biochips.”
Microelectron. J. (2019)
-
“Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology,
Design Automation, and Test Techniques.”
IEEE Trans. Biomed. Circuits Syst. (2019)
-
“Efficient Generation of Dilution Gradients With Digital Microfluidic
Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2019)
-
“Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer
Interconnection Architecture and Optimization Algorithms.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2019)
-
“Editorial TVLSI Positioning - Continuing and Accelerating an Upward
Trajectory.”
IEEE Trans. Very Large Scale Integr. Syst. (2019)
-
“Emerging Hardware Techniques and EDA Methodologies for Neuromorphic
Computing (Dagstuhl Seminar 19152).”
Dagstuhl Reports (2019)
-
“Reliability Hardening Mechanisms in Cyber-Physical Digital-Microfluidic
Biochips.”
ACM J. Emerg. Technol. Comput. Syst. (2018)
-
“Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array
Digital Microfluidic Biochip.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2018)
-
“Structural and Functional Test Methods for Micro-Electrode-Dot-Array
Digital Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2018)
-
“Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic
Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2018)
-
“Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic
Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2018)
-
“AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2018)
-
“Module Placement under Completion-Time Uncertainty in Micro-Electrode-Dot-Array
Digital Microfluidic Biochips.”
IEEE Trans. Multi Scale Comput. Syst. (2018)
-
“Flexible Droplet Routing in Active Matrix-Based Digital Microfluidic
Biochips.”
ACM Trans. Design Autom. Electr. Syst. (2018)
-
“Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP)
Workshop 2016.”
Integr. (2017)
-
“Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array
Digital Microfluidic Biochips.”
IEEE Trans. Biomed. Circuits Syst. (2017)
-
“Droplet Size-Aware and Error-Correcting Sample Preparation Using Micro-Electrode-Dot-Array
Digital Microfluidic Biochips.”
IEEE Trans. Biomed. Circuits Syst. (2017)
-
“Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic
Biochips.”
IEEE Trans. Biomed. Circuits Syst. (2017)
-
“Control-Layer Routing and Control-Pin Minimization for Flow-Based
Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2017)
-
“Adaptation of Biochemical Protocols to Handle Technology-Change for
Digital Microfluidics.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2017)
-
“Delay-Bounded Intravehicle Network Routing Algorithm for Minimization
of Wiring Weight and Wireless Transmit Power.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2017)
-
“Editorial.”
IEEE Trans. Very Large Scale Integr. Syst. (2017)
-
“Microfluidic Biochips: Bridging Biochemistry with Computer Science
and Engineering (NII Shonan Meeting 2017-1).”
NII Shonan Meet. Rep. (2017)
-
“A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose
Digital Microfluidic Biochips.”
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2016)
-
“Wash Optimization and Analysis for Cross-Contamination Removal Under
Physical Constraints in Flow-Based Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2016)
-
“Integrated Functional and Washing Routing Optimization for Cross-Contamination
Removal in Digital Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2016)
-
“Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid
Routing for Flow-Based Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2016)
-
“Leveraging Strategic Detection Techniques for Smart Home Pricing Cyberattacks.”
IEEE Trans. Dependable Secur. Comput. (2016)
-
“Optimization of 3D Digital Microfluidic Biochips for the Multiplexed
Polymerase Chain Reaction.”
ACM Trans. Design Autom. Electr. Syst. (2016)
-
“Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio
Matching.”
ACM Trans. Design Autom. Electr. Syst. (2016)
-
“Obstacle-Avoiding Wind Turbine Placement for Power Loss and Wake Effect
Optimization.”
ACM Trans. Design Autom. Electr. Syst. (2016)
-
“Guest Editors’ Introduction: Microfluidics: Design and Test Solutions
for Enabling Biochemistry on a Chip.”
IEEE Des. Test (2015)
-
“Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic
Biochips.”
IEEE Des. Test (2015)
-
“Storage and Caching: Synthesis of Flow-Based Microfluidic Biochips.”
IEEE Des. Test (2015)
-
“Design and Optimization of a Cyberphysical Digital-Microfluidic Biochip
for the Polymerase Chain Reaction.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2015)
-
“A Novel Analog Physical Synthesis Methodology Integrating Existent
Design Expertise.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2015)
-
“Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic
Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2015)
-
“An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic
Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2015)
-
“ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting
and Progressive Fixing in PCB Routing.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2015)
-
“Design of Microfluidic Biochips (Dagstuhl Seminar 15352).”
Dagstuhl Reports (2015)
-
“Design Automation for Digital Microfluidic Biochips.”
IPSJ Trans. Syst. LSI Des. Methodol. (2014)
-
“Placement optimization of flexible TFT circuits with mechanical
strain and temperature consideration.”
ACM J. Emerg. Technol. Comput. Syst. (2014)
-
“NBTI tolerance and leakage reduction using gate sizing.”
ACM J. Emerg. Technol. Comput. Syst. (2014)
-
“Biochip Synthesis and Dynamic Error Recovery for Sample Preparation
Using Digital Microfluidics.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
-
“Exploring Feasibilities of Symmetry Islands and Monotonic Current
Paths in Slicing Trees for Analog Placement.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
-
“Biochemistry Synthesis on a Cyberphysical Digital Microfluidics Platform
Under Completion-Time Uncertainties in Fluidic Operations.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
-
“Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained
EWOD Chips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
-
“ACER: An Agglomerative Clustering Based Electrode Addressing and
Routing Algorithm for Pin-Constrained EWOD Chips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
-
“Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test
Generation, and Experimental Demonstration.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
-
“Pulsed-Latch Utilization for Clock-Tree Power Optimization.”
IEEE Trans. Very Large Scale Integr. Syst. (2014)
-
“Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips.”
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2013)
-
“Bus-driven floorplanning with thermal consideration.”
Integr. (2013)
-
“Error Recovery in Cyberphysical Digital Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
-
“Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic
Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
-
“1-D Cell Generation With Printability Enhancement.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
-
“A Reliability-Oriented Placement Algorithm for Reconfigurable Digital
Microfluidic Biochips Using 3-D Deferred Decision Making Technique.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
-
“An ILP-Based Routing Algorithm for Pin-Constrained EWOD Chips With
Obstacle Avoidance.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
-
“Real-Time Error Recovery in Cyberphysical Digital-Microfluidic Biochips
Using a Compact Dictionary.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
-
“Bus-driven floorplanning with bus pin assignment and deviation minimization.”
Integr. (2012)
-
“A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2012)
-
“A Reagent-Saving Mixing Algorithm for Preparing Multiple-Target Biochemical
Samples Using Digital Microfluidics.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2012)
-
“Reliability-Driven Power/Ground Routing for Analog ICs.”
ACM Trans. Design Autom. Electr. Syst. (2012)
-
“Load-balanced clock tree synthesis with adjustable delay buffer insertion
for clock skew reduction in multiple dynamic supply voltage designs.”
ACM Trans. Design Autom. Electr. Syst. (2012)
-
“A Two-Stage Integer Linear Programming-Based Droplet Routing Algorithm
for Pin-Constrained Digital Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2011)
-
“An Effective and Efficient Framework for Clock Latency Range Aware
Clock Network Synthesis.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2011)
-
“A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing
EWOD Chips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2011)
-
“A Contamination Aware Droplet Routing Algorithm for the Synthesis
of Digital Microfluidic Biochips.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2010)
-
“PIXAR: A performance-driven X-architecture router based on a novel
multilevel framework.”
Integr. (2009)
-
“Multilevel routing with jumper insertion for antenna avoidance.”
Integr. (2006)
-
“Crosstalk- and performance-driven multilevel full-chip routing.”
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2005)
Conferences
-
“Mixed-Type Wafer Failure Pattern Recognition.”
In ASP-DAC (2023)
-
“A Global Optimization Algorithm for Buffer and Splitter Insertion
in Adiabatic Quantum-Flux-Parametron Circuits.”
In ASP-DAC (2023)
-
“BOMIG: A Majority Logic Synthesis Framework for AQFP Logic.”
In DATE (2023)
-
“Scalable Scan-Chain-Based Extraction of Neural Network Models.”
In DATE (2023)
-
“SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital
Microfluidic Biochips.”
In ACM Great Lakes Symposium on VLSI (2023)
-
“GAT-based Concentration Prediction for Random Microfluidic Mixers
with Multiple Input Flow Rates.”
In ACM Great Lakes Symposium on VLSI (2023)
-
“JRouter: A Multi-Terminal Hierarchical Length-Matching Router under
Planar Manhattan Routing Model for RSFQ Circuits.”
In ACM Great Lakes Symposium on VLSI (2023)
-
“Security Closure of IC Layouts Against Hardware Trojans.”
In ISPD (2023)
-
“NR-Router: Non-Regular Electrode Routing with Optimal Pin Selection
for Electrowetting-on-Dielectric Chips.”
In ASP-DAC (2022)
-
“Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based
Digital Microfluidic Biochips with Multiple Faults.”
In ASP-DAC (2022)
-
“A Lab-Based Investigation of Reaction Time and Reading Performance
using Different In-Vehicle Reading Interfaces during Self-Driving.”
In UI (2022)
-
“Functionality matters in netlist representation learning.”
In DAC (2022)
-
“GNN-based concentration prediction for random microfluidic mixers.”
In DAC (2022)
-
“PPATuner: pareto-driven tool parameter auto-tuning in physical design
via gaussian process transfer learning.”
In DAC (2022)
-
“TRADER: A Practical Track-Assignment-Based Detailed Router.”
In DATE (2022)
-
“Trojan Insertions of Fully Programmable Valve Arrays.”
In ETS (2022)
-
“Multi-Package Co-Design for Chiplet Integration.”
In ICCAD (2022)
-
“CoMUX: Combinatorial-Coding-Based High-Performance Microfluidic Control
Multiplexer Design.”
In ICCAD (2022)
-
“CARBEN: Composite Adversarial Robustness Benchmark.”
In IJCAI (2022)
-
“Robust Roadside Physical Adversarial Attack Against Deep Learning
in Lidar Perception Modules.”
In AsiaCCS (2021)
-
“A Multi-Commodity Network Flow Based Routing Algorithm for Paper-Based
Digital Microfluidic Biochips.”
In ASP-DAC (2021)
-
“Interference-Free Design Methodology for Paper-Based Digital Microfluidic
Biochips.”
In ASP-DAC (2021)
-
“ATM: A High Accuracy Extracted Timing Model for Hierarchical Timing
Analysis.”
In ASP-DAC (2021)
-
“Robustness of Neuromorphic Computing with RRAM-based Crossbars and
Optical Neural Networks.”
In ASP-DAC (2021)
-
“"One-Shot" Reduction of Additive Artifacts in Medical Images.”
In BIBM (2021)
-
“3D-Adv: Black-Box Adversarial Attacks against Deep Learning Models
through 3D Sensors.”
In DAC (2021)
-
“Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic
Biochips.”
In DATE (2021)
-
“An Efficient Programming Framework for Memristor-based Neuromorphic
Computing.”
In DATE (2021)
-
“Concentration Gradients Enhancement of Christmas-Tree Structure Based
on a Look-Up Table.”
In ACM Great Lakes Symposium on VLSI (2021)
-
“An Optimal Algorithm for Splitter and Buffer Insertion in Adiabatic
Quantum-Flux-Parametron Circuits.”
In ICCAD (2021)
-
“BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic
Lab-on-a-Chip Systems.”
In ICCAD (2021)
-
“Relative-Scheduling-Based High-Level Synthesis for Flow-Based Microfluidic
Biochips.”
In ICCAD (2021)
-
“Parallel Droplet Control in MEDA Biochips using Multi-Agent Reinforcement
Learning.”
In ICML (2021)
-
“Ct Image Denoising With Encoder-Decoder Based Graph Convolutional
Networks.”
In ISBI (2021)
-
“A standalone, programmable digital microfluidics system with multiplexor
interface logic.”
In MED (2021)
-
“Ensemble Learning Based Electric Components Footprint Analysis.”
In MLCAD (2021)
-
“Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction
Co-Optimization.”
In VLSI-DAT (2021)
-
“Robust Adversarial Objects against Deep Learning Models.”
In AAAI (2020)
-
“Beyond Digital Domain: Fooling Deep Learning Based Recognition System
in Physical World.”
In AAAI (2020)
-
“Do Noises Bother Human and Neural Networks In the Same Way? A Medical
Image Analysis Perspective.”
In BIBM (2020)
-
“Transfer Learning-Based Microfluidic Design System for Concentration
Generation\(_∗\).”
In DAC (2020)
-
“Statistical Training for Neuromorphic Computing using Memristor-based
Crossbars Considering Process Variations and Noise.”
In DATE (2020)
-
“Reliable and Robust RRAM-based Neuromorphic Computing.”
In ACM Great Lakes Symposium on VLSI (2020)
-
“HTcatcher: Finite State Machine and Feature Verifcation for Large-scale
Neuromorphic Computing Systems.”
In ACM Great Lakes Symposium on VLSI (2020)
-
“PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow
Microfluidic Biochips.”
In ICCAD (2020)
-
“ASAP: An Analytical Strategy for AQFP Placement.”
In ICCAD (2020)
-
“Countering Variations and Thermal Effects for Accurate Optical Neural
Networks.”
In ICCAD (2020)
-
“Adaptive Droplet Routing in Digital Microfluidic Biochips Using Deep
Reinforcement Learning.”
In ICML (2020)
-
“Transfer Learning without Knowing: Reprogramming Black-box Machine
Learning Models with Scarce Data and Limited Resources.”
In ICML (2020)
-
“Zero-Shot Medical Image Artifact Reduction.”
In ISBI (2020)
-
“A Survey of DMFBs Security: State-of-the-Art Attack and Defense.”
In ISQED (2020)
-
“Watermarking for Paper-Based Digital Microfluidic Biochips.”
In ITC-Asia (2020)
-
“Footprint Classification of Electric Components on Printed Circuit
Boards.”
In MLCAD (2020)
-
“CloudLeak: Large-Scale Deep Learning Models Stealing Through Adversarial
Examples.”
In NDSS (2020)
-
“Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array
biochips.”
In ASP-DAC (2019)
-
“Autonomous vehicle routing in multiple intersections.”
In ASP-DAC (2019)
-
“A General Cache Framework for Efficient Generation of Timing Critical
Paths.”
In DAC (2019)
-
“MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly
Constrained Control Ports.”
In DAC (2019)
-
“Vehicle Sequence Reordering with Cooperative Adaptive Cruise Control.”
In DATE (2019)
-
“Physical Synthesis of Flow-Based Microfluidic Biochips Considering
Distributed Channel Storage.”
In DATE (2019)
-
“Block-Flushing: A Block-based Washing Algorithm for Programmable
Microfluidic Devices.”
In DATE (2019)
-
“Open-Source Incubation Ecosystem for Digital Microfluidics - Status
and Roadmap: Invited Paper.”
In ICCAD (2019)
-
“VOM: Flow-Path Validation and Control-Sequence Optimization for
Multilayered Continuous-Flow Microfluidic Biochips.”
In ICCAD (2019)
-
“Cloud Columba: Accessible Design Automation Platform for Production
and Inspiration: Invited Paper.”
In ICCAD (2019)
-
“Supervised-Learning Congestion Predictor For Routability-Driven Global
Routing.”
In VLSI-DAT (2019)
-
“Sound valve-control for programmable microfluidic devices.”
In ASP-DAC (2018)
-
“Multi-level droplet routing in active-matrix based digital-microfluidic
biochips.”
In ASP-DAC (2018)
-
“Mechanical strain and temperature aware design methodology for thin-film
transistor based pseudo-CMOS logic array.”
In ASP-DAC (2018)
-
“Digital Rights Management for Paper-Based Microfluidic Biochips.”
In ATS (2018)
-
“Columba S: a scalable co-layout design automation tool for microfluidic
large-scale integration.”
In DAC (2018)
-
“Design-for-testability for continuous-flow microfluidic biochips.”
In DAC (2018)
-
“Pump-aware flow routing algorithm for programmable microfluidic devices.”
In DATE (2018)
-
“Multi-terminal routing with length-matching for rapid single flux
quantum circuits.”
In ICCAD (2018)
-
“Multi-channel and fault-tolerant control multiplexing for flow-based
microfluidic biochips.”
In ICCAD (2018)
-
“Test generation for microfluidic fully programmable valve arrays (FPVAs)
with heuristic acceleration.”
In ICICDT (2018)
-
“Design Automation and Test for Flow-Based Biochips: Past Successes
and Future Challenges.”
In ISVLSI (2018)
-
“More Effective Randomly-Designed Microfluidics.”
In ISVLSI (2018)
-
“A Comprehensive Security System for Digital Microfluidic Biochips.”
In ITC-Asia (2018)
-
“SOLAR: Simultaneous optimization of control-layer pins placement
and channel routing in flow-based microfluidic biochips.”
In VLSI-DAT (2018)
-
“Piracy prevention of digital microfluidic biochips.”
In ASP-DAC (2017)
-
“On reliability hardening in cyber-physical digital-microfluidic biochips.”
In ASP-DAC (2017)
-
“Hamming-distance-based valve-switching optimization for control-layer
multiplexing in flow-based microfluidic biochips.”
In ASP-DAC (2017)
-
“Close-to-optimal placement and routing for continuous-flow microfluidic
biochips.”
In ASP-DAC (2017)
-
“Reservoir and mixer constrained scheduling for sample preparation
on digital microfluidic biochips.”
In ASP-DAC (2017)
-
“Transport or Store?: Synthesizing Flow-based Microfluidic Biochips
using Distributed Channel Storage.”
In DAC (2017)
-
“Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics
Considering Hybrid-Scheduling.”
In DAC (2017)
-
“Testing microfluidic Fully Programmable Valve Arrays (FPVAs).”
In DATE (2017)
-
“Fast architecture-level synthesis of fault-tolerant flow-based microfluidic
biochips.”
In DATE (2017)
-
“Scheduling and optimization of genetic logic circuits on flow-based
microfluidic biochips.”
In DATE (2017)
-
“Design-for-testability for paper-based digital microfluidic biochips.”
In DFT (2017)
-
“LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic
Biochips.”
In ACM Great Lakes Symposium on VLSI (2017)
-
“Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic
Biochips.”
In ISVLSI (2017)
-
“Thermal optimization for memristor-based hybrid neuromorphic computing
systems.”
In ASP-DAC (2016)
-
“Sequence-pair-based placement and routing for flow-based microfluidic
biochips.”
In ASP-DAC (2016)
-
“Congestion- and timing-driven droplet routing for pin-constrained
paper-based microfluidic biochips.”
In ASP-DAC (2016)
-
“A routability-driven flow routing algorithm for programmable microfluidic
devices.”
In ASP-DAC (2016)
-
“A Verification Guided Approach for Selective Program Transformations
for Approximate Computing.”
In ATS (2016)
-
“Placement optimization of cyber-physical digital microfluidic biochips.”
In BioCAS (2016)
-
“High-level synthesis for micro-electrode-dot-array digital microfluidic
biochips.”
In DAC (2016)
-
“Columba: co-layout synthesis for continuous-flow microfluidic biochips.”
In DAC (2016)
-
“Sieve-valve-aware synthesis of flow-based microfluidic biochips considering
specific biological execution limitations.”
In DATE (2016)
-
“How secure is split manufacturing in preventing hardware trojan?.”
In AsianHOST (2016)
-
“Control-fluidic CoDesign for paper-based digital microfluidic biochips.”
In ICCAD (2016)
-
“Error recovery in a micro-electrode-dot-array digital microfluidic
biochip?.”
In ICCAD (2016)
-
“Built-in self-test for micro-electrode-dot-array digital microfluidic
biochips.”
In ITC (2016)
-
“Design of Microfluidic Biochips: Connecting Algorithms and Foundations
of Chip Design to Biochemistry and the Life Sciences.”
In VLSID (2016)
-
“Test and diagnosis of paper-based microfluidic biochips.”
In VTS (2016)
-
“Design and optimization of 3D digital microfluidic biochips for the
polymerase chain reaction.”
In ASP-DAC (2015)
-
“Obstacle-avoiding wind turbine placement for power-loss and wake-effect
optimization.”
In ASP-DAC (2015)
-
“Intra-vehicle network routing algorithm for wiring weight and wireless
transmit power minimization.”
In ASP-DAC (2015)
-
“An EDA framework for large scale hybrid neuromorphic computing systems.”
In DAC (2015)
-
“Reliability-aware synthesis for flow-based microfluidic biochips by
dynamic-device mapping.”
In DAC (2015)
-
“PACOR: practical control-layer routing flow with length-matching
constraint for flow-based microfluidic biochips.”
In DAC (2015)
-
“Analog layout synthesis with knowledge mining.”
In ECCTD (2015)
-
“Testing of digital microfluidic biochips with arbitrary layouts.”
In ETS (2015)
-
“EDA Challenges for Memristor-Crossbar based Neuromorphic Computing.”
In ACM Great Lakes Symposium on VLSI (2015)
-
“Cyber-physical integration in programmable microfluidic biochips.”
In ICCD (2015)
-
“Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment.”
In ISPD (2015)
-
“SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained
EWOD Chips.”
In ISPD (2015)
-
“A general testing method for digital microfluidic biochips under physical
constraints.”
In ITC (2015)
-
“A network-flow-based optimal sample preparation algorithm for digital
microfluidic biochips.”
In ASP-DAC (2014)
-
“Wash optimization for cross-contamination removal in flow-based microfluidic
biochips.”
In ASP-DAC (2014)
-
“A topology-based ECO routing methodology for mask cost minimization.”
In ASP-DAC (2014)
-
“Reliability-Driven Pipelined Scan-Like Testing of Digital Microfluidic
Biochips.”
In ATS (2014)
-
“Control-layer optimization for flow-based mVLSI microfluidic biochips.”
In CASES (2014)
-
“An Efficient Bi-criteria Flow Channel Routing Algorithm For Flow-based
Microfluidic Biochips.”
In DAC (2014)
-
“Exact One-pass Synthesis of Digital Microfluidic Biochips.”
In DAC (2014)
-
“Practical Functional and Washing Droplet Routing for Cross-Contamination
Avoidance in Digital Microfluidic Biochips.”
In DAC (2014)
-
“A logic integrated optimal pin-count design for digital microfluidic
biochips.”
In DATE (2014)
-
“A thermal resilient integration of many-core microprocessors and main
memory by 2.5D TSI I/Os.”
In DATE (2014)
-
“Vulnerability assessment and defense technology for smart home cybersecurity
considering pricing cyberattacks.”
In ICCAD (2014)
-
“Efficient building identification using structural and spatial information
on mobile devices.”
In ICME Workshops (2014)
-
“Recent trends in chip-level design automation for digital microfluidic
biochips.”
In ISIC (2014)
-
“Reliability-driven chip-level design for high-frequency digital microfluidic
biochips.”
In ISPD (2014)
-
“Triangle-based process hotspot classification with dummification in
EUVL.”
In VLSI-DAT (2014)
-
“Tutorial T5: Microfluidic Biochips: Connecting VLSI and Embedded
Systems to the Life Sciences.”
In VLSID (2014)
-
“Test generation and design-for-testability for flow-based mVLSI microfluidic
biochips.”
In VTS (2014)
-
“A clique-based approach to find binding and scheduling result in flow-based
microfluidic biochips.”
In ASP-DAC (2013)
-
“Control synthesis for the flow-based microfluidic large-scale integration
biochips.”
In ASP-DAC (2013)
-
“A network-flow based valve-switching aware binding algorithm for flow-based
microfluidic biochips.”
In ASP-DAC (2013)
-
“A novel cell placement algorithm for flexible TFT circuit with mechanical
strain and temperature consideration.”
In ASP-DAC (2013)
-
“Design of cyberphysical digital microfluidic biochips under completion-time
uncertainties in fluidic operations.”
In DAC (2013)
-
“Lithography-aware 1-dimensional cell generation.”
In ECCTD (2013)
-
“Post-route refinement for high-frequency PCBs considering meander
segment alleviation.”
In ACM Great Lakes Symposium on VLSI (2013)
-
“Optimization of polymerase chain reaction on a cyberphysical digital
microfluidic biochip.”
In ICCAD (2013)
-
“Post-route alleviation of dense meander segments in high-performance
printed circuit boards.”
In ICCAD (2013)
-
“A rapid analog amendment framework using the incremental floorplanning
technique.”
In ISCAS (2013)
-
“On Producing Linear Dilution Gradient of a Sample with a Digital Microfluidic
Biochip.”
In ISED (2013)
-
“A top-down synthesis methodology for flow-based microfluidic biochips
considering valve-switching minimization.”
In ISPD (2013)
-
“Tutorial: Digital microfluidic biochips: Towards hardware/software
co-design and cyber-physical system integration.”
In SoCC (2013)
-
“Timing-aware clock gating of pulsed-latch circuits for low power design.”
In VLSI-DAT (2013)
-
“Testing of flow-based microfluidic biochips.”
In VTS (2013)
-
“An ILP-based obstacle-avoiding routing algorithm for pin-constrained
EWOD chips.”
In ASP-DAC (2012)
-
“A cyberphysical synthesis approach for error recovery in digital microfluidic
biochips.”
In DATE (2012)
-
“Voltage-aware chip-level design for reliability-driven pin-constrained
EWOD chips.”
In ICCAD (2012)
-
“Dictionary-based error recovery in cyberphysical digital-microfluidic
biochips.”
In ICCAD (2012)
-
“Performance-driven analog placement considering monotonic current
paths.”
In ICCAD (2012)
-
“Design methodology for sample preparation on digital microfluidic
biochips.”
In ICCD (2012)
-
“Integrated fluidic-chip co-design methodology for digital microfluidic
biochips.”
In ISPD (2012)
-
“A nonlinear optimization methodology for resistor matching in analog
integrated circuits.”
In VLSI-DAT (2012)
-
“An efficient algorithm of adjustable delay buffer insertion for clock
skew minimization in multiple dynamic supply voltage designs.”
In ASP-DAC (2011)
-
“Digital microfluidic biochips: recent research and emerging challenges.”
In CODES+ISSS (2011)
-
“Digital microfluidic biochips: functional diversity, more than moore,
and cyberphysical systems.”
In CODES+ISSS (2011)
-
“A distributed algorithm for layout geometry operations.”
In DAC (2011)
-
“Progressive network-flow based power-aware broadcast addressing for
pin-constrained digital microfluidic biochips.”
In DAC (2011)
-
“PRICE: Power reduction by placement and clock-network co-synthesis
for pulsed-latch designs.”
In ICCAD (2011)
-
“Reliability-oriented broadcast electrode-addressing for pin-constrained
digital microfluidic biochips.”
In ICCAD (2011)
-
“Pulsed-latch-based clock tree migration for dynamic power reduction.”
In ISLPED (2011)
-
“Thermal-aware bus-driven floorplanning.”
In ISLPED (2011)
-
“A SAT-based routing algorithm for cross-referencing biochips.”
In SLIP (2011)
-
“Recent research and emerging challenges in design and optimization
for digital microfluidic biochips.”
In SoCC (2011)
-
“Automated Physical Design of Microchip-Based Capillary Electrophoresis
Systems.”
In VLSI Design (2011)
-
“Bus-pin-aware bus-driven floorplanning.”
In ACM Great Lakes Symposium on VLSI (2010)
-
“A network-flow based pin-count aware routing algorithm for broadcast
electrode-addressing EWOD chips.”
In ICCAD (2010)
-
“Digital microfluidic biochips: A vision for functional diversity
and more than moore.”
In ICCAD (2010)
-
“A two-stage ILP-based droplet routing algorithm for pin-constrained
digital microfluidic biochips.”
In ISPD (2010)
-
“Fast Legalization for Standard Cell Placement with Simultaneous Wirelength
and Displacement Minimization.”
In VLSI-SoC (Selected Papers) (2010)
-
“Fast legalization for standard cell placement with simultaneous wirelength
and displacement minimization.”
In VLSI-SoC (2010)
-
“A contamination aware droplet routing algorithm for digital microfluidic
biochips.”
In ICCAD (2009)
-
“A fast routability- and performance-driven droplet routing algorithm
for digital microfluidic biochips.”
In ICCD (2009)
-
“OAL: An obstacle-aware legalization in standard cell placement with
displacement minimization.”
In SoCC (2009)
-
“A Performance-Driven Multilevel Framework for the X-Based Full-Chip
Router.”
In PATMOS (2008)
-
“Multilevel full-chip routing for the X-based architecture.”
In DAC (2005)
-
“Multilevel routing with antenna avoidance.”
In ISPD (2004)
-
“Multilevel routing with jumper insertion for antenna avoidance.”
In SoCC (2004)
-
“A Fast Crosstalk- and Performance-Driven Multilevel Routing System.”
In ICCAD (2003)
Books
-
“Hardware/Software Co-Design and Optimization for Cyberphysical Integration
in Digital Microfluidic Biochips.”
(2015)
-
“Full-Chip Nanometer Routing Techniques.”
(2007)